1. Field of the Invention
This invention relates to the manufacture of semiconductor devices. More specifically, it relates to semiconductor devices containing fuses that are disposed in a compact interconnect structure and a method for disconnecting them.
2. Background of the Related Art
Custom electronic devices which are made from standard components suffer from several disadvantages. Since several components are required to implement such a custom device, more circuit board space is required than if a custom or semi-custom integrated circuit had been used in place of the standard components. This makes the overall size of the device larger and more expensive. Furthermore, the assembly process is longer, more costly, and prone to reworks or scrap, since more components are used. Further, a larger number of components usually requires more power consumption, which means a larger, heavier, and more expensive power supply. Therefore, the overall size, weight, and cost of the resulting custom device may make it unappealing to the consumer or not competitive when compared to a similar product offered by another company. Therefore, custom or application-specific integrated circuits (ASICs) are frequently used to implement new circuit designs in the place of standard components.
There are several types of ASICs which are available, depending on size, power, and programmability requirements, and volume of devices used. Fully custom devices offer the lowest cost and least amount of power consumption, but are only economical in very large quantities because of the costs of a custom mask set and engineering design time. Semi-custom devices such as gate arrays require a smaller number of custom masks and design time as compared to fully custom devices, but have a larger die size, cost more to produce, and are typically used when needed quantities are not quite as large. Similarities exist in custom and semi-custom devices in that both have relatively long lead times to produce prototypes and production volumes, and the designs are expensive and time consuming to change. Since the non-recurring costs are so large, it is not economical to produce them in small quantities. Other non-custom devices, such as programmable array logic (PALs), field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs), are fabricated as unprogrammed xe2x80x9cblanksxe2x80x9d which are programmed by the end user as packaged units or after installation onto a circuit board. These non-custom devices have a lower cost basis for smaller quantities, since no custom masks are required. The lead time to produce prototypes and production quantities is short, since the programming is performed near the end of the manufacturing cycle. They are also useful for designs which are expected to undergo revisions, since virtually no programmed material needs to be inventoried. However, these non-custom devices have the drawback of requiring a relatively large amount of die area dedicated to circuitry to perform the programming, and to signal paths to provide flexibility in routing, therefore they are more expensive to fabricate and don""t achieve the same programmable capacity as custom devices and gate arrays. In some cases, they also use more power and are slower.
Programming of the non custom programmable devices is sometimes accomplished through the use of disconnectable fuses. In this specification, the word fuse will be used to refer to fuses, anti-fuses, disconnection points, disconnectable links, or any combination of these terms. In certain types of programmable devices using electrically disconnectable or connectable fuses, the fuses in the device which define how the circuit is configured are accessed through the I/O pins on the device package. For techniques which require joining conductive regions together (for example, shorting a P/N junction), an excessive amount of current relative to normal operating conditions is passed through the junction, shorting it and allowing current to pass freely. To disconnect a conductive line, a fuse element in an undesired conduction path is subjected to enough current to heat it to its melting point, causing structural breakdown and creating a disconnection. Both of these methods require a relatively large amount of current to program the device. The transistors for generating these large currents in conventional MOS devices require large channel widths. Furthermore, a certain amount of heat insulation area is required around the fuses to prevent thermal damage to neighboring circuitry. This makes it difficult to achieve high device packing densities using these programming methods. Other devices have fuses which are disconnected through the use of a laser or other radiant energy beam device (hereinafter referred to as a xe2x80x9claserxe2x80x9d). For these devices, the laser is used to disconnect the fuses near the end of or after the conclusion of the fabrication process. These laser programmable devices have a smaller die size than the electrically programmable devices, and don""t require expensive precision custom masks and long lead times like the custom and semi-custom devices. The laser programmable devices are also economical to produce in smaller quantities compared to custom devices.
In addition to using fuses for the customization of an integrated circuit to give it specific circuit or electrical characteristics, fuses have also been used to (1) repair non-functional devices through the selective deletion of defective portions of the circuitry, or by substituting functional redundant circuitry for the defective portions of the circuitry; and (2) mark the device for identification of characteristics in a manner that is readable visually or electrically, for example serialization of the integrated circuit, or how the device has been configured by the laser.
FIG. 1 shows an array of fuses that can be disconnected by a laser. Fuse body 2 on fuse 1 is irradiated by laser beam 7, which has an energy distribution that is approximately radial Gaussian in nature. This energy distribution results in an effective laser spot size 6, that is the area of the beam which has an energy sufficient to disrupt active circuit elements. This disruption can be physical damage which causes the device to be non-functional, or it could cause performance degradation, such as silicon crystal dislocation which causes current leakage. The two characteristics which define the area requirements for a fuse, also called the fuse cell, are the pitch of the fuses in a group, and the length of the fuse. These two dimensions have a direct bearing on how much die area the fuse cell occupies, and thus the overall die size. The pitch 5 of the fuse cell is the distance from the center of one fuse to the center of the nearest neighboring fuse. This dimension is controlled by the requirement that the spot size 6 not disrupt any other fuses, and is conventionally calculated by adding the diameter of the spot size 6 and two times the maximum expected alignment error in the placement of the spot. The length 8 of the fuse is the sum of the length of fuse body 2 and fuse terminals 3. The length 8 of the fuse 1 is controlled by the need to isolate the thermal energy transmitted to the fuse by the laser from interconnect lines 4 attached to the fuse. Another influence to the area requirements of the fuse is whether circuitry can be routed underneath or in close proximity to the fuse. Most design rules specify that all of the area underneath of the fuse, and a certain area around it, be free of active circuitry to protect it from damage. Some designs provide for a barrier at another level between the fuses and the active circuitry and thus utilize some of the area.
As is also well known in the prior art, laser type fuses can alternatively be disconnectable by photolithographic techniques combined with etching to remove a section of the fuse, thus forming a disconnection. Photoresist layer 21 in FIG. 2 is patterned to make a hole 22 in the photoresist over the fuse 24. Well-known etching techniques are then used to etch through the fuse 24, completing the disconnection. As can be seen from FIG. 2, the disconnection can be made cleanly and thoroughly without a risk of damage to any underlying circuitry 25, which would not typically be routed under the fuse, but is shown here to illustrate that such routing can take place if desired. FIG. 3 illustrates that a smaller disconnection hole 31 on fuse 32 permits a smaller pitch 5. Since the thermal isolation requirements are not needed when using photolithographic techniques, the length of the fuse can also be shortened. The above-mentioned methods of disconnecting fuses can be used, in varying degrees, to reduce required fuse cell area and thus permit a smaller fuse cell and an advantageously smaller die. Accordingly, it is desirable to have a fuse design that makes most efficient use of these disconnection methods in order to increase the packing density of the fuses and produce a smaller die size, and a method of disconnecting that allows for such increased packing density.
It is an object of this invention to decrease the amount of space required for a fuse, or an array of fuses which form a specific circuit such as an AND array, thus reducing the overall size of the integrated circuit.
It is another object of the present invention to provide a method of disconnecting fuses that allows reduction in the overall size of the integrated circuit
The present invention achieves the above objects, among others, by providing a vertical fuse structure and method for customization of integrated circuits containing such a fuse structure that provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, the interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second inter-connect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.
Thus, the area required for the link is only as large as the cross-sectional area of the plug at the point of disconnection. Since the cross-sectional diameter of the plug is typically smaller than the width of the line connecting to it, the disconnection can be made without breaking the continuity of the line. This feature has benefits in optimizing the layout of the design to provide packing densities that would not be achievable with conventional fuse designs.